There has been used an electronic device, which controls voltage and current that are supplied to a load by turning on/off a semiconductor switching element. FIG. 1 illustrates an electronic device in the background art that is configured to drive a three-phase AC motor by some modifications of a driving circuit, as disclosed in JP-A-H07-226664.
The configuration of the electronic device illustrated in FIG. 1 will be briefly described. Although this electronic device is connected to a three-phase AC motor as a load 4, FIG. 1 illustrates only one of three phases. That is, in the case of driving the three-phase AC motor, the electronic device illustrated in FIG. 1 is used for each of three phases (the device typically called an inverter device or the like). In a unit 1 for one phase, a semiconductor switching element 2 (IGBT (Insulated Gate Bipolar Transistor) with a free-wheeling diode) of an upper arm and a semiconductor switching element 3 (IGBT with a free-wheeling diode) of a lower arm are connected in series between a power 9 for driving the load and a grounding point 10, and the connection point thereof is connected to one end of the load 4. The load 4 is configured to form a Y-connection or a delta-connection together with loads 4 connected to units of other two phases. Gate driving circuits having the same configuration are provided in the semiconductor switching element 2 of the upper arm and the semiconductor switching element 3 of the lower arm, respectively. Each of the gate driving circuits includes a transmission circuit 5 (5′), a reception circuit 6 (6′), and a gate driver 7 (7′), and a signal of the transmission circuit 5 (5′) is transmitted to the reception circuit 6 (6′) through a transformer 8 (8′). A control power 11 (11′) is connected to the reception circuit 6 (6′) and the gate driver 7 (7′).
The transmission circuit 5 (5′) is connected between a control power 12 (12′) and a grounding point 13 (that is isolated from the grounding point 10), and the transformer 8 (8′) and an NMOS transistor 14 (14′) are connected in series between the control power 12 (12′) and a grounding point 13. The gate terminal of the NMOS transistor 14 (14′) is connected to the output terminal of an AND circuit 17 (17′), and the input terminal of the AND circuit 17 (17′) is connected to an IN signal (IN′ signal) input terminal (control input signal terminal) and the output terminal of a pulse signal circuit 16 (16′).
Accordingly, when the IN (IN') signal (control input signal) is in an active state, the pulse signal from the pulse signal circuit 16 (16′) is input to the gate terminal of the NMOS transistor 14 (14′) through the AND circuit 17 (17′). If the pulse signal from the pulse signal circuit 16 (16′) is input to the gate terminal of the NMOS transistor 14 (14′), the NMOS transistor 14 (14′) is driven to be turned on/off, and a voltage that is caused by the pulse signal is applied to the primary winding of the transformer 8 (8′). On the other hand, a diode (rectifying element) 15 (15′) is connected to suppress the occurrence of overvoltage by flowing a reverse voltage that is generated in the primary winding of the transformer 8 (8′) as a circulating current. Since a voltage induced in the secondary winding of the transformer 8 (8′) is proportional to the primary winding, the reception circuit 6 (6′) generates a gate driving signal in response to this voltage as a trigger signal. The gate driving signal from the reception circuit 6 (6′) is amplified by the gate driver 7 (7′), and the semiconductor switching element 2 (3) is driven to be turned on/off by the amplified gate driving signal.
FIG. 2 illustrates a gate driving circuit using the semiconductor switching element 2 (3) of FIG. 1 that transmits the signal of the transmission circuit 5 (5′) to the reception circuit 6 (6′) through the transformer 8 (8′). Here, since the gate driving circuits using the semiconductor switching element 2 of the upper arm and the semiconductor switching element 3 of the lower arm have the same configuration, for example, only the upper arm that is extracted from FIG. 1 is illustrated in FIG. 2. Further, in FIG. 2, the IN signal input terminal IN, the pulse signal circuit 16, and the AND circuit 17 are integrally described as a pulse signal circuit 18. Further, the reception circuit 6, the gate driver 7, the semiconductor switching element 2, the load 4, the power 9 for driving the load, the control power 11, and the grounding point 10 are integrally described as a load 19. FIG. 2 as described above illustrates one of main portions the background art related to this disclosure.
FIG. 3 is a waveform diagram illustrating the operation of a circuit illustrated in FIG. 2. The pulse signal circuit 18 outputs a continuous square-wave pulse as shown as the “output signal of the pulse signal circuit 18” in FIG. 3. If the “IN signal” is at a high level, as can be seen from FIG. 1, the AND circuit 17 passes the pulse signal from the pulse signal circuit 16 to drive the NMOS transistor. As shown in FIG. 3, when the “IN signal” is at a high level and the “pulse signal” is at a high level, the NMOS transistor 14 is turned on to apply a voltage to the transformer 8, and thus current flow through the transformer 8. In this case, a positive voltage is generated in the “voltage of the transformer 8” corresponding to the rising of the “current of the transformer 8”, and a negative voltage is generated in the “voltage of the transformer 8” corresponding to the falling of the “current of the transformer 8”. The reception circuit 6 and the gate driver 7 on the secondary side of the transformer are driven by the signal only when the “voltage of the transformer 8” is positive, and then supply the gate driving signal for turning on the semiconductor switching element 2, as shown in the “IGBT gate-source voltage” at the bottom of FIG. 3